When positioned in an external magnetic field, the resistance of a magneto-resistive transducer varies in response to variations of the magnetic field over time. Magneto-resistive transducers have been used as read heads in magnetic disk drives and are being more commonly used for this purpose.
A typical magneto-resistive transducer includes a strip of nickel-iron metallization on a silicon substrate. A preamplifier coupled to the strip applies a bias voltage across the strip (to cause current flow through the strip), and while doing so generates an amplified signal indicative of the potential difference across the strip. The amplified signal then undergoes further processing.
A typical preamplifier of this type is shown in FIG. 1A, and a portion of the FIG. 1A circuit is shown in FIG. 1. In FIG. 1, the magneto-resistive transducer is represented as a resistor having resistance R.sub.MR. The drain of PMOS transistor M1 is coupled to one end of the transducer, the source of M1 is coupled to the top rail (at potential V.sub.CC), the drain of NMOS transistor M2 is coupled to the other end of the transducer, and the source of M2 is coupled to the bottom rail (at potential V.sub.EE). The transducer is biased by asserting bias potentials V.sub.BP and V.sub.BN to the gates of transistors M1 and M2, thereby applying a bias potential across the transducer and causing current I.sub.MR to flow through the transducer (and through transistors M1 and M2). The magnitudes of the bias potentials V.sub.BP and V.sub.BN are chosen as a function of the transducer resistance (e.g., the transducer resistance in the presence of no magnetic field) and other factors to optimize system performance.
The potential difference (V.sub.MR) across the transducer is amplified to generate differential output OUT.sub.P, OUT.sub.N (indicative of the potential difference across the transducer), by an amplifier comprising NPN bipolar transistors Q.sub.P1 and Q.sub.P2 (whose bases are coupled to opposite ends of the transducer), NPN bipolar transistors Q.sub.P3 and Q.sub.P4 (whose bases are coupled to receive bias voltages VB3 and VB4), current source 3 coupled to the common emitters of transistors Q.sub.P1 and Q.sub.P3, and current source 4 coupled to the common emitters of transistors Q.sub.P2 and Q.sub.P4. The output signal OUT.sub.P, OUT.sub.N is produced at the collectors of transistors Q.sub.P1 and Q.sub.P2.
With reference to FIG. 1A, we next describe typical circuitry for producing the above-mentioned bias potentials V.sub.BP, V.sub.BN, V.sub.B3, and V.sub.B4 which are employed in FIG. 1.
In FIG. 1A, circuit 40 (which includes above-discussed transistor M1) is a current source which is biased, by potential V.sub.SETP asserted at the output of digital-to-analog converter 61, to function as the source of the current I.sub.MR which flows through transducer R.sub.MR.
Op amp 62, NPN bipolar transistor Q62, and resistor R.sub.REF (connected as shown in FIG. 1A) provide reference current I.sub.REF to digital-to-analog converter ("DAC") 61, when reference potential V.sub.REF is asserted at the noninverting input of op amp 62. To control the output of DAC 61, control logic 60 asserts control bits to DAC 61. In response to the control bits and reference current I.sub.REF the output of DAC 61 is at the potential V.sub.SETP (and circuit 40 draws current I.sub.DAC-RMR therefrom). In response to potential V.sub.SETP, circuit 40 maintains the gate of transistor M1 at a desired bias potential V.sub.BP.
More specifically, circuit 40 includes PMOS transistors M0 and M1 and capacitor C.sub.P (connected as shown in FIG. 1A), transconductance amplifier 50 (whose inverting input is coupled to the output of DAC 61 and whose noninverting input is coupled to the drain of transistor M0), resistor R.sub.SETP (coupled between ground and the inverting input of amplifier 50), and resistor R.sub.SNSP (coupled between the drain of M0 and ground). The gates of transistors M1 and M0 are coupled to the output of amplifier 50, so that the output potential of amplifier 50 is the bias potential V.sub.BP for the gate of transistor M1. Since transistor M0 has characteristics which match those of transistor M1, the current at the drain of M0 is proportional (with a known proportionality factor) to the current at the drain of M1, and the noninverting terminal of amplifier 50 thus receives feedback (from the drain of transistor M0) indicative of the drain current of transistor M1. In response to this feedback, amplifier 50 maintains the bias potential V.sub.BP at a level, determined by the reference potential V.sub.SETP, which will maintain the current through the transducer at a desired nominal level.
Circuit 42 includes NMOS transistor M2, capacitor C.sub.N, and resistors R.sub.CM, R.sub.DIF1, and R.sub.DIF2 connected as shown in FIG. 1A (with R.sub.CM connected between ground and Node 1, R.sub.DIF1 connected between one end of the transducer and Node 1, and R.sub.DIF2 connected between the other end of the transducer and Node 1), and transconductance amplifier 52 whose inverting input is coupled to receive bias potential V.sub.CM-SETN. The noninverting input of amplifier 52 is coupled to Node 1, and thus is maintained at a potential (above ground) equal to the common mode voltage of the transducer, (V.sub.RMRP +V.sub.RMRN)/2, where V.sub.RMRP -V.sub.RMRN is the voltage across the transducer (since R.sub.DIF1 =R.sub.DIF2 R.sub.CM /2, with R.sub.DIF1 typically equal to 20 KOhms). Thus, amplifier 52 (whose output is coupled to the gate of transistor M2) forces the gate of M2 to remain at a bias potential V.sub.BN, determined by the reference potential V.sub.CM-SETN, which will maintain the common mode voltage of the transducer at a desired level (typically at or near ground potential).
Still with reference to FIG. 1A, the abovediscussed differential output OUT.sub.P, OUT.sub.N of the FIG. 1 circuit (which is indicative of the potential difference across the transducer and is produced at the collectors of transistors Q.sub.P1 and Q.sub.P2) undergoes amplification in second stage amplifier 51. The resulting amplified differential output (V.sub.o2N, V.sub.o2P) is asserted to a third stage (not shown).
The amplified differential output (V.sub.o2N, V.sub.o2P) is also asserted to the inputs of transconductance amplifier 54. In response, transconductance amplifier 54 asserts a first output having potential V.sub.B3 to the base of transistor Q.sub.P3 and a second output having potential V.sub.B4 to the base of transistor Q.sub.P4. Current source 56 is coupled between the base of transistor Q.sub.P3 and the top rail, and current source 58 is coupled between the base of transistor Q.sub.P4 and the top rail, as shown. Thus, amplifier 54 determines the difference between bias potentials V.sub.B3 and V.sub.B4. Circuit 45 (which includes transconductance amplifier 55) sets the common mode voltage V.sub.B3 +V.sub.B4)/2 to an appropriate level determined by bias potential V.sub.CM-SET (which is asserted to the inverting input of transconductance amplifier 55). The noninverting input of transconductance amplifier 55 is coupled between resistors R.sub.B1 and R.sub.B2, and resistors R.sub.B1 and R.sub.B2 are connected in series between the base of Q.sub.P3 and the base of QP.sub.4. The output of amplifier 55 is connected to the common gates of NMOS transistors Q54 and Q55. The drain of Q55 is coupled to the base of Q.sub.P4, and capacitor C.sub.B is coupled between the base of Q.sub.P3 and the base of Q.sub.P4. Capacitor C.sub.BN is coupled between the output of amplifier 55 and the bottom rail.
It is well known that any of many different architectures are possible for implementing a preamplifier for a magneto-resistive transducer (e.g., the transducer shown in FIG. 1A whose resistance is R.sub.MR). All the architectures (including that of FIG. 1A) must perform the following functions: generate an appropriate bias current through the transducer; maintain the common mode voltage of the transducer ((V2+V1)/2, where V2-V1 is the voltage across the transducer) at an appropriate level to prevent electrical discharge to the disk (or other object being sensed) and to allow voltage headroom (source-to-drain or collector-to-emitter voltage) for the various current source and amplifier transistors; and bias the amplifier transistors at appropriate voltages to sense and amplify the differential voltage across the transducer while minimizing the d.c. or low frequency component of the preamplifier's differential output voltage.
Although the transducer's resistance R.sub.MR varies with time during normal circuit operation, conventional circuitry for determining the magnitudes of bias potentials V.sub.BP and V.sub.BN cannot adjust the magnitudes of bias potentials V.sub.BP and V.sub.BN (in real time) during normal circuit operation to maintain optimized performance despite the varying transducer resistance. It would be desirable to generate a resistance signal indicative of the transducer resistance during normal operation (in addition to the conventional preamplifier output which is indicative of the potential difference across the transducer; not the transducer's resistance). Such a resistance signal could be used as feedback to circuitry for maintaining optimal biasing of the transducer.
It should be appreciated that the conventional preamplifier output (which is indicative of voltage across the transducer; not the transducer' resistance) is indicative only of high frequency components of the voltage across the transducer, since the preamplifier acts as a high pass filter. Such a conventional output signal gives no indication of the d.c. component of the bias voltage for the transducer (or the low frequency components of such bias voltage). To indicate the d.c. bias voltage for the transducer, the standard practice in the prior art is to provide a separate, buffered d.c. output which can be either an analog voltage (indicative of the d.c. bias across the transducer) or the output of an analog-to-digital converter (in response to such an analog voltage). The output of such an analog-to-digital converter can be accessed through a serial port by an external microcontroller running appropriate firmware. It is conventional to employ firmware to deduce the resistance of the transducer by processing a signal indicative of the current through the transducer (usually selected by the firmware through a digital-to-analog converter coupled with the preamplifier), and the buffered d.c. output indicative of d.c. bias voltage across the transducer. However, this prior art technique is cumbersome and inaccurate. It would be desirable to generate a resistance signal indicative (accurately) of the instantaneous value of transducer resistance during normal operation (while the transducer is biased and in the presence of a magnetic field), so that the resistance signal can be used as feedback to circuitry for maintaining optimal biasing of the transducer.
When implementing magnetic disk drive systems (which use a magneto-resistive transducer as read heads), if the disk drive systems do not continuously optimize the d.c. bias voltage for the magneto-resistive transducer in real time, it is possible to make a one-time adjustment to the d.c. bias voltage as a result of determining part-to-part variation in the resistance of magneto-resistive heads. Such an adjustment could be performed during the manufacture of the disk drive system. However, it would be preferable during normal operation of such a disk drive system to monitor the resistance of the transducer and employ feedback to maintain optimal biasing of the transducer.
In resistive transducers other than magneto-resistive transducers, the resistance of the transducer varies in response to a parameter being sensed. As in the case of magneto-resistive transducers, it would often be useful (during preamplification of the potential difference across any of the other types of resistive transducers) to generate a signal indicative of the transducer' resistance (in addition to the preamplifier output which is indicative of the potential difference across the transducer).